EPM5032-15 查看數據表（PDF） - Altera Corporation

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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See Operating Requirements for Altera Devices Data Sheet in this data book.

(2) Minimum DC input is –0.3 V. During transitions, the inputs may undershoot to

–2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions.

(3) Numbers in parentheses are for industrial-temperature-range versions.

(4) Maximum VCC rise time for MAX 5000 devices is 10 ms.

(5) Typical values are for TA = 25° C and VCC = 5.0 V.

(6) The IOH parameter refers to high-level TTL output current; the IOL parameter refers

to low-level TTL output current.

Figure 6 shows typical output drive characteristics of MAX 5000 devices.

Figure 6. Output Drive Characteristics of MAX 5000 Devices

100

IOL

80

60

VCC = 5.0 V

Room Temp.

40

IOH

20

0.45 1

2

3

4

5

VO Output Voltage (V)

Timing Model

MAX 5000 EPLD timing can be analyzed with the MAX+PLUS II

software, with a variety of other industry-standard EDA simulators and

timing analyzers, or with the timing model shown in Figure 7. MAX 5000

EPLDs have fixed internal delays that allow the user to determine the

worst-case timing for any design. MAX+PLUS II provides timing

simulation, point-to-point delay prediction, and detailed timing analysis

for system-level performance evaluation.

322

Altera Corporation

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