EPM5032-15 查看數據表（PDF） - Altera Corporation
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EPM5032-15 Datasheet PDF : 36 Pages
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MAX 5000 Programmable Logic Device Family Data Sheet
EPM5032 AC Operating Conditions Note (1)
External Timing Parameters
Symbol
Parameter
t PD1
t PD2
t SU
tH
t CO1
t CH
t CL
t ASU
t AH
t ACO1
t ACH
t ACL
t ODH
t CNT
f CNT
t ACNT
f ACNT
f MAX
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Output data hold time after clock
Min. global clock period
Max. internal global clock frequency
Min. array clock period
Max. internal array clock frequency
Max. clock frequency
Conditions
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Note (3)
C1 = 35 pF (2)
Note (4)
Note (4)
Note (5)
EPM5032-15 EPM5032-20 EPM5032-25
Min Max Min Max Min Max Unit
15
20
25 ns
15
20
25 ns
9
12
15
ns
0
0
0
ns
10
12
15 ns
6
7
8
ns
6
7
8
ns
5
6
8
ns
5
6
8
ns
15
18
22 ns
6
7
9
ns
7
9
11
ns
1
1
1
ns
13
16
20 ns
76.9
62.5
50
MHz
13
16
20 ns
76.9
62.5
50
MHz
83.3
71.4
62.5
MHz
326
Altera Corporation
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