EPM5032-15 查看數據表（PDF） - Altera Corporation

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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

...and More

Features

General

Description

s Programming support with Altera’s Master Programming Unit

(MPU) or programming hardware from other manufacturers

s Additional design entry and simulation support provided by EDIF,

LPM, Verilog HDL, VHDL, and other interfaces to popular EDA tools

from manufacturers such as Cadence, Data I/O, Exemplar, Mentor

Graphics, MINC, OrCAD, Synopsys, VeriBest, and Viewlogic

The MAX 5000 family combines innovative architecture and advanced

process technologies to offer optimum performance, flexibility, and the

highest logic-to-pin ratio of any general-purpose programmable logic

device (PLD) family. The MAX 5000 family provides 600 to 3,750 usable

gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to

83.3 MHz. See Table 2.

Table 2. MAX 5000 Timing Parameter Availability

Device

EPM5032

EPM5064

EPM5128

EPM5130

EPM5192

15 ns

v

Speed (tPD1)

20 ns 25 ns

v

v

v

v

v

v

30 ns

v

v

35 ns

v

v

v

v

The MAX 5000 architecture supports 100% TTL emulation and

high-density integration of multiple SSI, MSI, and LSI logic functions. For

example, an EPM5192 device can replace over 100 74-series devices; it can

integrate complete subsystems into a single package, saving board area

and reducing power consumption. MAX 5000 EPLDs are available in a

wide range of packages (see Table 3), including the following:

s Windowed ceramic and plastic dual in-line (CerDIP and PDIP)

s Windowed ceramic and plastic J-lead chip carrier (JLCC and PLCC)

s Windowed ceramic pin-grid array (PGA)

s Plastic small-outline integrated circuit (SOIC)

s Ceramic and plastic quad flat pack (CQFP and PQFP)

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Altera Corporation

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