AD7304 查看數據表（PDF） - Analog Devices
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AD7304 Datasheet PDF : 20 Pages
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AD7304/AD7305
+5V
VREF = 10V p-p
f = 20kHz
+5V
0V
0V
–5V
(OUT)
–5V
VOUT = 10V p-p
(IN)
Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz
TIMING SPECIFICATIONS
@ VDD = 3 V or 5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, VSS ≤ VREF ≤ VDD, –40°C < TA < +85°C/+125°C, unless otherwise noted.
Table 2.
Parameter
INTERFACE TIMING SPECIFICATIONS1, 2
AD7304 Only
Clock Width High
Clock Width Low
Data Setup
Data Hold
Load Pulse Width
Load Setup
Load Hold
Clear Pulse Width
Select
Deselect
AD7305 Only
Data Setup
Data Hold
Address Setup
Address Hold
Write Width
Load Pulse Width
Load Setup
Load Hold
Symbol
tCH
tCL
tDS
tDH
tLDW
tLD1
tLD2
tCLWR
tCSS
tCSH
tDS
tDH
tAS
tAH
tWR
tLDW
tLS
tLH
3 V ± 10%
70
70
50
30
70
40
40
60
30
60
60
30
60
30
60
60
60
30
5 V ± 10%
55
55
40
20
60
30
30
60
20
40
40
20
40
20
50
50
40
20
±5 V ± 10%
55
55
40
20
60
30
30
60
20
40
40
20
40
20
50
50
40
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1 These parameters are guaranteed by design and not subject to production testing.
2 All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Rev. C | Page 4 of 20
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