ETL9345 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ETL9345

4-BIT NMOS MICROCONTROLLERS

STMicroelectronics 

ET L9 44 4/ 94 4 5 –ET L 9 344 / 9 3 45

4. All successive transfer of control instructions

and successive LBIs have been completed

(e.g., if the main program is executing a JP in-

struction which transfers program control to

another JP instruction, the interrupt will not be

acknowledged until the second JP instruction

has been executed.

c. Upon acknowledgement of an interrupt, the skip

logic status is saved and later restored upon pop-

ping of the stack. For example, if an interrupt oc-

curs during the execution of ASC (Add with

Carry, Skip on Carry) instruction which results in

carry, the skip logic status is saved and program

control is transferred to the interrupt servicing

routine at hex address 0FF. At the end of the in-

terrupt routine, a RET instruction is executed to

”pop” the stack and return program control to the

instruction following the original ASC. At this

time, the skip logic is enabled and skips this in-

struction because of the previous ASC carry.

Subroutines and LQIDinstructions should not be

nested within the interrupt service routine, since

their popping the stack will enable any previously

saved main program skips, interfering with the

orderly execution of the interrupt routine.

d. The first instruction of the interrupt routine at hex

address 0FF must be a NOP.

e. A LEI instruction can be put immediately before

the RET to re-enable interrupts.

INITIALIZATION

The Reset Logic will initialize (clear) the device upon

power-up if the power supply rise time is less than

1ms and greater than 1µs. If the power supply rise

time is greater than 1ms, the user use provide an ex-

ternal RC network and diode to the RESET pin as

shown below. If the RC network is not used, the RE-

SET pin must be pulled up to VCC either by the in-

ternal load or by an external resistor (≥40kΩ) to VCC.

The RESET pin is configured as a Schmitt trigger in-

put. Initialization will occur whenever a logic ”0” is

applied to the RESET input, provided it stays low for

at least three instruction cycle times.

Power-up Clear Circuit.

Upon initialization, the PC register is cleared to 0

(ROM address 0) and the A, B, C, D, EN, and G re-

gisters are cleared. The SK output is enabled as a

SYNC output, providing a pulse each instruction cy-

cle time. Data Memory (RAM) is not cleared upon i-

nitialization. The first instruction at address 0 must

be a CLRA.

OSCILLATOR

There are three basic clock oscillator configurations

available as shown by figure 4.

a. Crystal Controlled Oscillator. CKI and CKO

are connected to an external crystal. The instruc-

tion cycle time equals the crystal frequency divi-

ded by 32 (optional by 16 or 8).

b. External Oscillator. CKI is an external clock in-

put signal. The external frequency is divided by

32 (optional by 16 or 8) to give the instruction cy-

cle time. CKO is now available to be used as the

RAM power supply (VR), as a general purpose

input, or as a SYNC input.

c. RC Controlled Oscillator. CKI is configured as

a single pin RC controlled Schmitt trigger oscil-

lator. The instruction cycle equals the oscillation

frequency divided by 4. CKO is available as the

RAM power supply (VR) or as a general purpose

input.

11/27

Share Link: