ETL9444 查看數據表（PDF） - STMicroelectronics

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ETL9444

4-BIT NMOS MICROCONTROLLERS

STMicroelectronics 

Figure 3a : Synchronization Timing.

ET L9 44 4/ 94 4 5 –ET L 9 344 / 9 3 45

FUNCTIONAL DESCRIPTION

A block diagram of the ETL9444 is given in figure 1.

Data paths are illustrated in simplified form to depict

how the various logic elements communicate with

each other in implementing the instruction set of the

device. Positive logic is used. When a bit is set, it is

a logic ”1” (greater than 2 volts). When a bit is reset,

it is a logic ”0” (less than 0.8 volts).

All functional references to the ETL9444/L9445 also

apply to the ETL9344/L9345.

PROGRAM MEMORY

Program Memory consists of a 2048 byte ROM. As

can be seen by an examination of the

ETL9444/L9445 instruction set, these words may be

program instructions, program data or ROM addres-

sing data. Because of the special characteristics as-

sociated with the JP, JSRP, JID, and LQID

instructions, ROM must often be thought of as being

organized into 32 pages of 64 words each.

ROM addressing is accomplished by a 11-bit PC re-

gister. Its binary value selects one of the 2048 8-bit

words contained in ROM. A new address is loaded

into the PC register during each instruction cycle.

Unless the instruction is a transfer of control instruc-

tion, the PC register is loaded with the next sequen-

tial 11-bit binary count value. Three levels of

subroutine nesting are implemented by the 11-bit

subroutine save registers, SA, SB, and SC ; provi-

ding a last-in, first-out (LIFO) hardware subroutine

stack.

ROM instruction words are fetched, decoded and

executed by the Instruction Decode, Control and

Skip Logic circuitry.

DATA MEMORY

Data memory consists of a 512-bit RAM, organized

as 8 data registers of 16 4-bit digits. RAM addres-

sing is implemented by a 7-bit B register whose up-

per 3 bits (Br) select 1 of 8 data registers and lower

4 bits (Bd) select 1 of 16 4-bit digits in the selected

data register. While the 4-bit contents of the selected

RAM digit (M) is usually loaded into or from, or ex-

changed with, the A register (accumulator), it may

also be loaded into or from the Q latches or loaded

from the L ports. RAM addressing may also be per-

formed directly by the LDD and XAD instructions ba-

sed upon the 7-bit contents of the operand field of

these instructions. The Bd register also serves as a

source register for 4-bit data sent directly to the D

outputs.

INTERNAL LOGIC

The 4-bit A register (accumulator) is the source and

destination register for most I/O, arithmetic, logic

and data memory access operations. It can also be

used to load the Br and Bd portions of the B register,

to load and input 4 bits of the 8-bit Q latch data, to

input 4 bits of the 8-bit L I/O port data and to perform

data exchanges with the SIO register.

A 4-bit adder performs the arithmetic and logic func-

tions, storing its results in A. It also outputs a carry

bit to the 1-bit C register, most often employed to in-

dicate arithmetic overflow. The C register, in

conjunction with the XAS instruction and the EN re-

gister, also serves to control the SK output. C can

be outputted directly to SK or can enable SK to be

a sync clock each instruction cycle time. (See XAS

instruction and EN register description, below).

Four general-purpose inputs, IN3-IN0, are provided.

The D register provides 4 general-purpose outputs

and is used as the destination register for the 4-bit

contents of Bd. The D outputs can be directly

connected to the digits of a multiplexed LED display.

The G register contents are outputs to 4 general-

purpose bidirectional I/O ports. G I/O ports can be

directly connected to the digits of a multiplexed LED

display.

The Q register is an internal, latched, 8-bit register,

used to hold data loaded to or from M and A, as well

as 8-bit data from ROM. Its contents are output to

the L I/O ports when the L drivers are enabled under

program control (See LEI instruction).

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