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A5317P 查看數據表(PDF) - Fuji Electric

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A5317P Datasheet PDF : 17 Pages
First Prev 11 12 13 14 15 16 17
FA531X series
2. Disabling overload shutdown function
As shown in Figure 24, connect a 11kresistor between the
FB pin and ground. Then, the CS pin voltage does not rise
high enough to reach the reference voltage (7.0V) of the latch
comparator, and the IC does not enter the OFF latch mode.
With this connection, the overvoltage shutdown function is
available.
3. Setting soft start period and OFF latch delay
independently
Figure 25 shows a circuit for setting the soft start period and
OFF latch delay independently. In this circuit, capacitance CS
determines the soft start period, and capacitance CL
determines the OFF latch delay. If the overload shutdown and
overvoltage shutdown functions raise the CS pin voltage to
around 5V, zener diode Zn becomes conductive to charge CL.
The OFF latch delay can be thus prolonged by CL.
4. Laying out VCC and ground lines
Figure 26 and 27 show the recommended layouts of VCC and
ground lines. The bold lines represent paths carrying large
currents. The lines must have an adequate thickness.
5.Sink current setting for CS terminal
A sink current to CS terminal must be satisfied the following
condition to prevent from the malfunction which uncontrolled
pulse output generates at OUT terminal when latch-mode
protection should be operated for overvoltage.
65µA < Ics(sink) < 500µA at Vcs= 6.5(V)
Ics(sink) : Sink current to CS terminal
Example (for the circuit shown in Fig. 28 )
Ics(sink) = (28(V)–18(V)– 6.5(V) )/7.5(k)
Լ 467 (µA) < 500 (µA)
Fig. 25 Independent setting of soft-start period
and OFF latch delay
Fig. 26 Vcc line and ground line (1) for FA5310B/11B/16/17
Fig. 24 Disabling overload shutdown function
11
Fig. 27 Vcc line and ground line (2) for FA5314/15
CS
VCC
7.5k18V Zener diode
Under 500µA
Fig. 28 Setting sink current for CS terminal

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