FAH4820 查看數據表（PDF） - Fairchild Semiconductor
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FAH4820 Datasheet PDF : 14 Pages
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I2C DC Electrical Characteristics
TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted.
Symbol
Parameter
VIL Low-Level Input Voltage
VIH High-Level Input Voltage
VOL
Low-Level Output Voltage at 3 mA Sink Current
(Open-Drain or Open-Collector)
IIH High-Level Input Current of Each I/O Pin, Input Voltage = VDD
IIL Low-Level Input Current of Each I/O Pin, Input Voltage = 0 V
Fast Mode (400 kHz)
Min.
Max.
Unit
-0.3
0.6
V
1.3
V
0
0.4
V
-1
1
µA
-1
1
µA
I2C AC Electrical Characteristics
Symbol
Parameter
Fast Mode (400 kHz)
Min.
Max.
Unit
fSCL SCL Clock Frequency
0
400
kHz
tHD;STA Hold Time (Repeated) START Condition
0.6
µs
tLOW Low Period of SCL Clock
1.3
µs
tHIGH High Period of SCL Clock
0.6
µs
tSU;STA Set-up Time for Repeated START Condition
0.6
µs
tHD;DAT
tSU;DAT
tr
tf
Data Hold Time
Data Set-up Time(1)
Rise Time of SDA and SCL Signals(2)
Fall Time of SDA and SCL Signals(2)
0
0.9
µs
100
ns
20+0.1Cb 300
ns
20+0.1Cb 300
ns
tSU;STO Set-up Time for STOP Condition
0.6
µs
tBUF Bus-Free Time between STOP and START Conditions
1.3
µs
tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
1. A Fast-Mode I2C Bus® device can be used in a Standard-Mode I2C bus system, but the requirement tSU;DAT
≥250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
Serial Data (SDA) line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C Bus
specification) before the SCL line is released.
2. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
allowed according to the I2C specification.
Figure 4. Definition of Timing for Full-Speed Mode Devices on the I2C Bus
© 2013 Fairchild Semiconductor Corporation
FAH4820 • 1.0.0
5
www.fairchildsemi.com
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