FAH4820MPX 查看數據表（PDF） - Fairchild Semiconductor
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FAH4820MPX Datasheet PDF : 14 Pages
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write operation should be terminated by a STOP
condition from the master (see Figure 7).
As with reading, the master can write multiple bytes by
continuing to send data. The FAH4820 increments the
pointer by one and accepts data for the next register.
The master indicates the last data byte by issuing a
STOP condition.
Read / Write Diagrams
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
START
(from Master)
Slave Address
(from Master)
ACK
(from Slave)
Figure 5.
Data
(from Slave)
NACK
(from Master)
I2C Read
STOP
(from Master)
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
START
(from Master)
Slave Address
(from Master)
ACK
(from Slave)
Figure 6.
Data
(from Slave)
ACK
(from Master)
I2C Multiple Byte Read
Data
(from Slave)
NACK
(from Master)
STOP
(from Master)
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 R/W ACK P7 P6 P5 P4 P3 P2 P1 P0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
START
(from Master)
Slave Address
(from Master)
ACK
(from Slave)
Pointer
(from Master)
ACK
(from Slave)
Figure 7. I2C Write
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 R/W ACK P7 P6 P5 P4 P3 P2 P1 P0 ACK
Data
(from Master)
ACK
(from Slave)
STOP
(from Master)
A7 A6 A5 A4
START
(from Master)
Slave Address
(from Master)
ACK
(from Slave)
Pointer
(from Master)
ACK
(from Slave)
Repeat START Slave Address
(from Master)
(from Master)
A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK
Figure 8.
Slave Address
(from Master)
ACK
(from Slave)
I2C Write Followed by Read
Data
(from Slave)
NACK
(from Master)
STOP
(from Master)
Digital Interface
The I2C-compatible interface is used to program the FAH4820 as listed in the below register configurations. The I2C
address of the FAH4820 is 0x06.
Binary
00000110
Hex
0x06
© 2013 Fairchild Semiconductor Corporation
FAH4820 • 1.0.0
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