DS2433S 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2433S

4 kbit 1-Wire EEPROM

Dallas Semiconductor -> Maxim Integrated 

DS2433 MEMORY MAP Figure 5

ADDRESS

0000H TO

001FH

0020H TO

003FH

0040H TO

01DFH

1FE0H TO

01FFH

32-BIT INTERMEDIATE STORAGE SCRATCHPAD

32-BYTE FINAL STORAGE EEPROM

32-BYTE FINAL STORAGE EEPROM

FINAL STORAGE EEPROM

32-BYTE FINAL STORAGE EEPROM

PAGE 0

PAGE 1

PAGE 2

TO PAGE 14

PAGE 15

DS2433

ADDRESS REGISTER Figure 6

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S)

(READ ONLY)

AA 1) PF E4 E3 E2 E1 E0

1) THIS BIT WILL ALWAYS BE 0.

READ MEMORY [F0H]

The read memory command may be used to read the entire memory. After issuing the command, the

master must provide the 2-byte target address. After the two bytes, the master reads data beginning from

the target address and may continue until the end of memory, at which point logic 1’s will be read. It is

important to realize that the target address registers will contain the address provided. The ending

offset/data status byte is unaffected.

The hardware of the DS2433 provides a means to accomplish error-free writing to the memory section.

To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is

recommended to packetize data into data packets of the size of one memory page each. Such a packet

would typically store a 16-bit CRC with each page of data to insure rapid, error-free data transfers that

eliminate having to read a page multiple times to determine if the received data is correct or not. (See the

Book of DS19xx iButton Standards, Chapter 7 or Application Note 114 for the recommended file

structure.)

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