FAN5078D3 查看數據表（PDF） - Fairchild Semiconductor
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FAN5078D3 Datasheet PDF : 18 Pages
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5V DUAL
5V Dual "dip"
4.4V
5V MAIN
S3#O
S3#I
Figure 5. S3 to S0 Transition: 5V DUAL
This dip can also occur in 5V USB and 3.3V-ALW if 5V and
3.3V are not fully charged before the 5V MAIN pin exceeds
its threshold. To eliminate the dip, add delay to the 5V MAIN
pin, as shown below. The 5V MAIN pin does not supply
power to the IC; it is only used to monitor the voltage level of
the 5V MAIN supply. The pin has a pull-down resistor
impedance of about 62K and therefore requires a low value
RDLY resistor (see Figure 6 below).
+5MAIN
FROM
ATX
RDLY 5V MAIN 4
CDLY
Figure 6. Adding Delay to 5V MAIN
Another method of eliminating the potential for this dip is to
connect the ATX power supply PWR_OK signal to the 5V
MAIN pin. Some systems cannot tolerate the long delay for
PWR_OK (>100ms) to assert, so the solution in Figure 6
may be preferable.
If the PWR_OK signal is used, the voltage at the 5V MAIN
pin must reach the 5V MAIN threshold. Since the internal
pull-down resistance of the 5V MAIN pin is 62K, a low value
pull-up should be used. A lower current solution can also be
used by employing the 12V supply to provide adequate pull-
up capability. The circuit in Figure 7 requires that PWR_OK,
12V, and +5MAIN from the ATX are all up before allowing
the IC to go to S0.
10K
+12V
5V MAIN 4
5VS B
PWR_OK
Care should also be taken to ensure that 3.3V-ALW does not
glitch during the transition to S0. As shown in Figure 8, the
3.3V internal regulator turns off as soon as 5V MAIN crosses
its rising threshold, releasing S3#O. While the gate
capacitances of Q5, Q7, and Q3 charge sufficiently to turn
Q5 ON, the load current on 3.3-ALW is supplied by C12.
There is an initial “ESR step” of I3.3 x ESRC12, where I3.3 is
the 3.3-ALW load current. This is followed by a discharge of
C12 whose slope is proportional to I3.3 . To ensure that the
C12
drop in 3.3-ALW during this transition does not cause system
problems, use sufficiently low-ESR capacitors and a
sufficiently low value for R4 to ensure that 3.3-ALW remains
inside the required system tolerance.
3.3-ALW I3.3 x ESRC12
3.3V LDO
ON
OFF
S3#O
(Q5 gate)
4.4V
5V MAIN
S3#I
Figure 8. 3.3V-ALW Transition to S0
S5 to S5 M1 or S3: During S5 to S3 transition, the IC pulls
SBSW (or SBUSB# if enabled by S4ST#) LOW with a 500nA
current sink to limit inrush in Q4 if 5V MAIN is below its
UVLO threshold. At that time, 5V DUAL and 5V USB are
discharged. The limited gate drives control the inrush current
through Q4 or Q6 as they charge their respective load
capacitances on 5V DUAL and 5V USB, respectively.
Depending on the CGD of Q4 and Q6, the current available
from 5V SB, and the size of CIN and C15, C13, and C14 may
be omitted.
IQ4(INRUSH)
=
CIN • 5X10 −7
C13 + CGD(Q4)
IQ6(INRUSH)
=
C15 • 5X10−7
C14 + CGD(Q6)
(2)
If 5V MAIN is above its UVLO threshold, SBSW (or SBUSB# if
enabled by S4ST#) is pulled down with an impedance of
~150Ω. VDDQ and VTT do not start until 5V MAIN OK is true.
Figure 7. Using PWR_OK to Enable 5V MAIN
© 2008 Fairchild Semiconductor Corporation
11
FAN5078D3 • Rev. 1.0.0
www.fairchildsemi.com
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