FAN5078D3 查看數據表（PDF） - Fairchild Semiconductor
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FAN5078D3 Datasheet PDF : 18 Pages
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Pin Configuration
SBUSB#
S4ST#
SBSW
5V MAIN
VTT SNS
VTT OUT
24 23 22 21 20 19
P1 = GND
7 8 9 10 11 12
EN
S3#I
S3#O
3.3 ALW
VCC
PGOOD
Figure 4. 5x5mm MLP Package (θJA = 38°C/W)
(Connect P1 pad to GND)
Pin Definitions
Pin # Name Description
1
SBUSB#
USB Standby. Pulls LOW with constant current to limit slew rate in S3 if S4ST# is HIGH. Drives a
P-channel MOSFET to connect 5V SB to 5V USB.
2
S4ST# S4_STATE# Connect to system logic signal that enables 5V USB power in S3.
3
SBSW
Standby Switch. Drives the P-channel MOSFET to power 5V DUAL from 5V SB when in S3. HIGH in
S0 and S5.
4 5V MAIN 5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited.
5 VTT SNS VTT remote sense input.
6 VTT OUT VTT regulator power output.
7 VDDQ IN VDDQ Input from PWM. Connect to VDDQ output voltage. This is the VTT regulator power input.
8
BOOT
Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot
diode to VCC.
9
HDRV High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.
10
SW
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and low-side MOSFET drain.
11
ISNS
Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor
for current feedback and current limiting.
12
LDRV Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.
Power Good Flag. An open-drain output that pulls LOW when FB is outside of a ±10% range of the
13 PGOOD 0.9V reference or the VTT output is < 80% or > 110% of its reference. PGOOD goes LOW when the IC
is in the S5 state. The power-good signal from the PWM regulator enables the VTT regulator.
© 2008 Fairchild Semiconductor Corporation
5
FAN5078D3 • Rev. 1.0.0
www.fairchildsemi.com
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