FAN5078D3 查看數據表（PDF） - Fairchild Semiconductor

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FAN5078D3

Complete ACPI Compliant Power Solution for DDR3 Memory System

Fairchild Semiconductor 

Pin Definitions (Continued)

Pin # Name Description

14

VCC

VCC. Provides IC bias and gate drive power. The IC is held in standby until this pin is above the UVLO

threshold.

15 3.3 ALW 3.3V LDO Output. Internal LDO output. Turned OFF in S0; ON in S5 or S3.

16

S3#O

S3#O Output. Open-drain output that pulls the gate of the N-channel blocking MOSFETs LOW in S5

and S3. This pin goes HIGH (open) in S0.

17

S3#I

S3 Input. When LOW, turns off VTT and turns on the 3.3V regulator. Also causes S3#O to pull LOW to

turn off blocking switch Q3, as shown in Figure 1. PGOOD is LOW when S3#I is LOW.

18

EN

ENABLE. Typically tied to the system logic signal S5#. When this pin is LOW, the IC is in a low

quiescent current state, all regulators are OFF, and S3#O is LOW.

19,

P1

GND GROUND for the IC is tied to this pin and is also connected to P1.

20

ILIM Current Limit. A resistor from this pin to GND sets the current limit.

21

SS

Soft Start. A capacitor from this pin to GND programs the slew rate of the PWM and all LDOs during

initialization and transitions between states.

22

COMP

COMP. Output of the PWM error amplifier. Connect the compensation network between this pin and

FB.

23

FB

VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD, under-

voltage, and over-voltage protection and monitoring.

24

REF IN

VTT Reference. Input that provides the reference for the VTT regulator. A precision internal divider

from VDDQ IN (which can be overridden with external resistors) is provided.

© 2008 Fairchild Semiconductor Corporation

6

FAN5078D3 • Rev. 1.0.0

www.fairchildsemi.com

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