M27C4001-35B1TR 查看數據表（PDF） - STMicroelectronics

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M27C4001-35B1TR

4 Mbit (512Kb x 8) UV EPROM and OTP EPROM

STMicroelectronics 

M27C4001

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

M27C4001

Symbol Alt

Parameter

Test Condition

-70

-80/-90

Min Max Min Max

tAVQV

tACC

Address Valid to

Output Valid

E = VIL, G = VIL

70

80

tELQV

tCE

Chip Enable Low to

Output Valid

G = VIL

70

80

tGLQV

tOE

Output Enable Low to

Output Valid

E = VIL

35

40

tEHQZ (2)

tDF

Chip Enable High to

Output Hi-Z

G = VIL

0

30

0

30

tGHQZ (2)

tDF

Output Enable High to

Output Hi-Z

E = VIL

0

30

0

30

tAXQX

tOH

Address Transition to

Output Transition

E = VIL, G = VIL 0

0

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

-10/-12/-15

Min Max

100

100

50

0 30

0 30

0

Unit

ns

ns

ns

ns

ns

ns

Figure 5. Read Mode AC Waveforms

A0-A18

E

G

Q0-Q7

VALID

tAVQV

tGLQV

tELQV

tAXQX

VALID

tEHQZ

tGHQZ

Hi-Z

AI00724B

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

devices. The supply current, ICC, has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at

the output. The associated transient voltage peaks

can be suppressed by complying with the two line

output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceram-

ic capacitor be used on every device between VCC

and VSS. This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7µF bulk electrolytic capacitor should be

used between VCC and VSS for every eight devic-

es. The bulk capacitor should be located near the

power supply connection point. The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

6/17

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