M48Z512A(2006) 查看數據表（PDF） - STMicroelectronics

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M48Z512A
(Rev.:2006)

4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z512A M48Z512AY M48Z512AV

Operating modes

Figure 5. Chip Enable or Output Enable controlled, READ mode ac waveforms

A0-A18

E

G

DQ0-DQ7

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tAXQX

tEHQZ

tGHQZ

DATA OUT

1. WRITE Enable (W) = high.

Figure 6. Address controlled, READ mode ac waveforms

AI01221

A0-A18

DQ0-DQ7

tAVQV

tAVAV

DATA VALID

1. Chip Enable (E) and Output Enable (G) = low, WRITE Enable (W) = high.

tAXQX

AI01220

9/24

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