M48Z512AV 查看數據表（PDF） - STMicroelectronics

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M48Z512AV

4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z512A

M48Z512AY, M48Z512AV

4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM

Not recommended for new design

Features

■ Integrated, ultra low power SRAM, power-fail

control circuit, and battery

■ Conventional SRAM operation; unlimited

) WRITE cycles

t(s ■ 10 years of data retention in the absence of

c power

du ■ Automatic power-fail chip deselect and WRITE

ro protection

P ■ Two WRITE protect voltages:

te (VPFD = power-fail deselect voltage)

le – M48Z512A: VCC = 4.75 to 5.5 V;

4.5 V ≤ VPFD ≤ 4.75 V

so – M48Z512AY: VCC = 4.5 to 5.5 V;

b 4.2 V ≤ VPFD ≤ 4.5 V

O – M48Z512AV: VCC = 3.0 to 3.6 V;

- 2.8 V ≤ VPFD ≤ 3.0 V

t(s) ■ Battery internally isolated until power is applied

c ■ Pin and function compatible with JEDEC

u standard 512 K x 8 SRAMs

rod ■ PMDIP32 is an ECOPACK® package

■ RoHS compliant

Obsolete P – Lead-free second level interconnect

32

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PMDIP32 module

Description

The M48Z512A/Y/V ZEROPOWER® RAM is a

non-volatile, 4,194,304-bit static RAM organized

as 524,288 words by 8 bits. The devices combine

an internal lithium battery, a CMOS SRAM and a

control circuit in a plastic, 32-pin DIP module.

June 2011

Doc ID 5146 Rev 9

This is information on a product still in production but not recommended for new designs.

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