Operating modes
M48Z512A, M48Z512AY, M48Z512AV
Figure 4. Chip enable or output enable controlled, READ mode AC waveforms
A0-A18
tAVAV
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
ct(s) DQ0-DQ7
tGLQX
DATA OUT
rodu 1. WRITE enable (W) = high
P Figure 5. Address controlled, READ mode AC waveforms
olete A0-A18
t(s) - Obs DQ0-DQ7
tAVQV
tAVAV
DATA VALID
Obsolete Produc 1. Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
AI01221
tAXQX
AI01220
8/21
Doc ID 5146 Rev 9