VG26S17400EJ-5 查看數據表（PDF） - Vanguard International Semiconductor
零件编号
产品描述 (功能)
生产厂家
VG26S17400EJ-5 Datasheet PDF : 25 Pages
| |||
VIS
AC Characteristics
(Ta = 0 to + 70°C, VCC = 5V ±10% or 3.3V ±10%, VSS = 0V) * 1, * 2, * 3, * 4
Test conditions
• Output load : two TTL Loads and 100pF(VCC = 5.0V ±10%)
one TTL Load and 100pF(VCC = 3.3V ±10%)
• Input timing reference levels :
VIH = 2.4V, VlL = 0.8V (VCC = 5.0V ± 10%); VIH = 2.0V, VlL = 0.8V (VCC = 3.3V ±10%)
• Output timing reference levels :
VOH = 2.0V, VOL = 0.8V (VCC = 5V ±10%, 3.3V ±10%)
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
Read, Write, Read - Modify - Write and Refresh Cycles
(Common Parameters)
VG26 (V) (S) 17400E
Parameter
Symbol
-5
Min Max
-6
Unit
Min Max
Random read or write cycle time
tRC
90
- 110
- ns
RAS precharge time
tRP
30
- 40
- ns
CAS precharge time in normal mode
tCPN
10
- 10
- ns
RAS pulse width
tRAS
50 10000
60 10000 ns
CAS pulse width
tCAS
12 10000 15 10000 ns
Row address setup time
tASR
0
-
0
- ns
Row address hold time
tRAH
8
- 10
- ns
Column address setup time
tASC
0
-
0
- ns
Column address hold time
tCAH
8
- 10
- ns
RAS to CAS delay time
tRCD
12
37 14
45 ns
RAS to column address delay time
tRAD
10
25 12
30 ns
Column address to RAS lead time
tRAL
25
- 30
- ns
RAS hold time
tRSH
13
- 15
- ns
CAS hold time
tCSH
50
- 60
- ns
CAS to RAS precharge time
tCRP
5
-
5
- ns
OE to Din delay time
tOED
12
- 15
- ns
Transition time (rise and fall)
tT
1
50
1
50 ns
Refresh period
tREF
-
32
-
32 ms
Refresh period (S - Version)
tREF
-
128
-
128 ms
CAS to output in Low-Z
tCLZ
0
-
0
- ns
CAS delay time from Din
tDZC
0
-
0
- ns
OE delay time from Din
tDZO
0
-
0
- ns
Notes
5
6
7
8
9
10
11
Document : 1G5-0142
Rev.1
Page 10
Share Link: 