FIN3383 查看數據表（PDF） - Fairchild Semiconductor
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FIN3383 Datasheet PDF : 18 Pages
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Transmitter AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
tTCP
Transmit Clock Period
tTCH
Transmit Clock (TxCLKIn) HIGH Time
tTCL
Transmit Clock Low Time
tCLKT
TxCLKIn Transition Time (Rising and Failing)
tJIT
TxCLKIn Cycle-to-Cycle Jitter
tXIT
TxIn Transition Time
LVDS Transmitter Timing Characteristics
See Figure 5
(10% to 90%) See Figure 6
11.76
T
50.0
ns
0.35
0.5
0.65
T
0.35
0.5
0.65
T
1.0
6.0
ns
3.0
ns
1.5
6.0
ns
tTLH
tTHL
tSTC
tHTC
tTPDD
tTCCD
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
TxIn Setup to TxCLNIn
TxIn Holds to TCLKIn
Transmitter Power-Down Delay
Transmitter Clock Input to Clock Output Delay
Transmitter Clock Input to Clock Output Delay
See Figure 4
0.75
1.5
ns
0.75
1.5
ns
2.5
ns
See Figure 5 (f 85 MHz)
0
ns
See Figure 12, (Note 13)
100
ns
(TA 25qC and with VCC 3.3V)
See Figure 9
2.8
5.5
ns
6.8
Transmitter Output Data Jitter (f 40 MHz) (Note 14)
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
Transmitter Output Pulse Position of Bit 5
tTPPB6
Transmitter Output Pulse Position of Bit 6
Transmitter Output Data Jitter (f 65 MHz) (Note 14)
See Figure 16
1
a
fx7
0.25
0
0.25
ns
a0.25
a
a0.25
ns
2a0.25 2a 2a0.25 ns
3a0.25 3a 3a0.25 ns
4a0.25 4a 4a0.25 ns
5a0.25 5a 5a0.25 ns
6a0.25 6a 6a0.25 ns
tTPPB0
Transmitter Output Pulse Position of Bit 0
tTPPB1
Transmitter Output Pulse Position of Bit 1
tTPPB2
Transmitter Output Pulse Position of Bit 2
tTPPB3
Transmitter Output Pulse Position of Bit 3
tTPPB4
Transmitter Output Pulse Position of Bit 4
tTPPB5
Transmitter Output Pulse Position of Bit 5
tTPPB6
Transmitter Output Pulse Position of Bit 6
Transmitter Output Data Jitter (f 85 MHz) (Note 14)
See Figure 16
1
a
fx7
0.2
0
0.2
ns
a0.2
a
a0.2
ns
2a0.2
2a
2a0.2
ns
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
5a0.2
5a
5a0.2
ns
6a0.2
6a
6a0.2
ns
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
tJCC
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385 Transmitter Clock Out Jitter
(Cycle-to-Cycle)
See Figure 16
1
a
fx7
f 40 MHz
f 65 MHz
0.2
0
0.2
ns
a0.2
a
a0.2
ns
2a0.2
2a
2a0.2
ns
3a0.2
3a
3a0.2
ns
4a0.2
4a
4a0.2
ns
5a0.2
5a
5a0.2
ns
6a0.2
6a
6a0.2
ns
350
370
210
230
ps
See Figure 20
f 85 MHz
110
150
tTPLLS
Transmitter Phase Lock Loop Set Time (Note 15)
See Figure 22, (Note 14)
10.0
ms
Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and
Power-Down pin is above 1.5V.
Note 14: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 14). Figure 16 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
7
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