FIN3386MTDX 查看數據表（PDF） - Fairchild Semiconductor
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FIN3386MTDX
Fairchild Semiconductor
FIN3386MTDX Datasheet PDF : 21 Pages
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Transmitter AC Electrical Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
Parameter
tTCP Transmit Clock Period
tTCH Transmit Clock (TxCLKIn) HIGH Time
tTCL Transmit Clock LOW Time
tCLKT TxCLKIn Transition Time (Rising and Falling)
tJIT TxCLKIn Cycle-to-Cycle Jitter
tXIT TxIn Transition Time
LVDS Transmitter Timing Characteristics
tTLH
tTHL
tSTC
tHTC
tTPDD
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (20% to 80%)
TxIn Setup to TxCLNIn
TxIn Holds to TxCLNIn
Transmitter Power-Down Delay
tTCCD Transmitter Clock Input to Clock Output Delay
Transmitter Output Data Jitter (f=40MHz)(12)
tTPPB0 Transmitter Output Pulse Position of Bit 0
tTPPB1 Transmitter Output Pulse Position of Bit 1
tTPPB2 Transmitter Output Pulse Position of Bit 2
tTPPB3 Transmitter Output Pulse Position of Bit 3
tTPPB4 Transmitter Output Pulse Position of Bit 4
tTPPB5 Transmitter Output Pulse Position of Bit 5
tTPPB6 Transmitter Output Pulse Position of Bit 6
Transmitter Output Data Jitter (f=65MHz) (12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
Condition
Figure 9
(10% to 90%)
Figure 10
Min.
11.76
0.35
0.35
1.0
1.5
Typ.
T
0.50
0.50
Max.
50.00
0.65
0.65
Unit
ns
T
T
6.0
ns
3.0
6.0
ns
Figure 8
Figure 9
2.5
f=85MHz
0
Figure 14 (11)
(TA=25°C and
with VCC=3.3V)
2.8
Figure 13
0.75 1.50 ns
0.75
1.50
ns
ns
ns
100
ns
5.5
6.8
ns
Figure 20
a 1
f 7
-0.25
a-0.25
2a-0.25
3a-0.25
4a-0.25
5a-0.25
6a-0.25
0
0.25 ns
a
a+0.25 ns
2a 2a+0.25 ns
3a 3a+0.25 ns
4a 4a+0.25 ns
5a 5a+0.25 ns
6a 6a+0.25 ns
Figure 20
a 1
f 7
-0.2
a-0.2
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
0
0.2
ns
a
a+0.2 ns
2a 2a+0.2 ns
3a 3a+0.2 ns
4a 4a+0.2 ns
5a 5a+0.2 ns
6a 6a+0.2 ns
Continued on the following page…
© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
8
www.fairchildsemi.com
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