FIN212AC(2008) 查看數據表（PDF） - Fairchild Semiconductor
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FIN212AC
(Rev.:2008)
(Rev.:2008)
Fairchild Semiconductor
FIN212AC Datasheet PDF : 23 Pages
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Control Logic Circuitry
Mode PLL0 PLL1 S1 S0
0
X
X
00
1
1
0
01
1
0
0
01
1
X
X
01
2
1
0
10
2
0
0
10
2
X
X
10
3
1
0
11
3
0
0
11
3
X
X
11
Table 1. Control Logic Circuitry
DIRI
X
1
1
0
1
1
0
1
1
0
Description
Power-Down Mode
12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF
12-Bit Serializer, Over-0Clocked PLL, 4.7MHz to 13.3MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF
12-Bit Deserializer
[DIRI] Direction Logic: The FIN212 can be configured
as a 12-bit serializer or deserializer based on the state
of the DIRI signal. When DIRI is 1, the device is a
serializer. When DIRI is 0, the device is a deserializer.
The /DIRO signal is an inversion of the DIRI signal. The
/DIRO signal of the master can be used to drive the
DIRI signal of the slave in applications where the
interface needs to be turned around.
[S0, S1] Mode Select: The mode select signals, S1
and S0, are used for different purposes when the device
is a serializer or a deserializer. For the serializer, the
pins need to be set to the correct value of the input
CKREF Frequency range.
For the deserializer the signals are used to select an
edge rate value. The fastest edge rates correspond to
the highest frequency mode. This relationship is
maintained for all modes.
Mode #
DIRI=0
S1
S0
0
0
0
1
0
1
2
1
0
3
1
1
Table 2. Deserializer Edge Rates
Frequency
Range
Power-Down
FAST
SLOW
MEDIUM
[PLL0, PLL1] PLL Frequency Select Signals: The
PLL1 and PLL0 signals provide additional flexibility in
generating the serial clock frequency. The PLLn signals
only function when the device is a serializer (DIRI=1).
When the device is a slave, these pins are used for
pulse width adjustment.
Over-clocking mode is used when the input reference
clock has been implemented with significant spread
spectrum. Over-clocking allows the serializer to tolerate
a large amount of CKREF frequency spread.
No-Divide mode should be used for standard 8-bit pixel
interface where the STROBE and CKREF frequencies
are identical.
Divide-by-2 and Divide-by-3 modes are useful in
microcontroller interfaces where the CKREF frequency is
significantly higher than the required STROBE frequency.
DIRI=1
PLL1
PLL0
Serializer Frequency
Multiplier
0
0
7.3x
Over-clocking
0
1
7x
No Divide
1
0
3.5x
Divide by 2
1
1
2.3x
Table 3. Frequency Multipliers
Divide by 3
Internal STROBE Filter: When the PLL starts, the
STROBE signal is internally held off until the PLL is
locked. This prevents any spurious data from being
passed through the device.
[PWS0, PWS1] Pulse Width Adjust Circuitry: The
word clock strobe output (CKP) pulse width can be
adjusted through the PWS0 and PWS1 signals. The
signals can be used to lengthen the width of the LOW
pulse or invert the pulse in RGB applications with a 50%
duty cycle.
DIRI=0
PWS1 PWS0
Low Time
(Bits)
No Divide
Polarity (CKP
Read Edge)
0
0
7
LH
0
1
7
HL
1
0
13
LH
1
1
17
LH
Table 4. Pulse Width Adjust Circuitry at Serial
CLK Period
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.6
4
www.fairchildsemi.com
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