FIN212AC(2008) 查看數據表（PDF） - Fairchild Semiconductor

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FIN212AC
(Rev.:2008)

12-Bit Serializer Deserializer with Multiple Frequency Ranges

Fairchild Semiconductor 

Application Diagrams

The following application diagrams illustrate the most typical applications for the FIN212 device. Specific

configurations of the control pins may vary based on the needs of a given system. The following recommendations

are valid for all of the applications shown.

Baseband

Microprocessor

PIXEL CLK

DATA[7:0]

HSYNC

VSYNC

/RES

FIN212

Serializer

VDD1

D3

E4 F4

VDDP VDDS/A

VDD

2.775

FIN212

Deserializer

VDD2

E4 F4

D3

VDDS/A VDDP

A6 CKREF

B5 STROBE

NC C1 CKP

CKP C1

STROBE B5

CKREF A6

B3:E1

E2

F1

G1:F2

VDD1

F6

G3

G4

DP[8:1]

DP[9] CKSO+ C5

DP[10] CKSO- C6

DP[12:11]

DSO+/DSI- D6

DSO-/DSI+ D5

CKSI - E6 NC

DIRI

CKSI+ E5 NC

PLL1

PLL0

/DIRO B6 NC

S1

S0

G5

G6

DP[8:1] B3:E1

E5 CKSI+

E6 CKSI-

DP[9] E2

DP[10] F1

D6

DP[12:11] G1:F2

DSO-/DSI+

NC

D5

NC C6

DSO+/DSI-

CKSO- XTRM

A3

NC C5 CKSO+

DIRI F6

NC B6 /DIRO

PWS1 G3

PWS0 G4

S1

G5

S0

G6

LCD Display

Module

PIXEL CLK

DATA[7:0]

HSYNC

VSYNC

/RES

Figure 4. 8-Bit RGB Application (Example Shows BGA 42-Pin Package)

Serializer Configuration:

ƒ PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range

ƒ PLL Divide Mode: Over-Clocked Mode (PLL1=PLL0=0); 7.3 Serial Frequency Multiplier

Deserializer Configuration:

ƒ Edge Rate Mode: Medium MODE 3 (S1=S0=1)

ƒ Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period

ƒ Pixel CLK is used to STROBE Display

ƒ Pin number for BGA packages

© 2006 Fairchild Semiconductor Corporation

FIN212AC Rev. 1.0.6

8

www.fairchildsemi.com

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