FIN212AC(2008) 查看數據表（PDF） - Fairchild Semiconductor

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FIN212AC
(Rev.:2008)

12-Bit Serializer Deserializer with Multiple Frequency Ranges

Fairchild Semiconductor 

Application Diagrams (Continued)

Baseband

Microprocessor

Camera

Interface

MASTER CLK

PIXEL CLK

YUV[7:0]

HSYNC

VSYNC

/RES

FIN212

Deserializer

FIN212

Serializer

VDD1

D3

E4 F4

VDDP VDDS/A

VDD

2.775

VDD2

E4 F4

D3

VDDS/A VDDP

A6 CKREF

B5 STROBE

C1 CKP

CKP C1

STROBE B5

CKREF A6

B3:E1 DP[8:1]

NC

E2

F1

G1:F2

DP[9] CKSO+

DP[10] CKSO-

DP[12:11]

C5

C6

DSO+/DSI- D6

DSO-/DSI+ D5

A3 XTRM

F6 DIRI

CKSI - E6

CKSI+ E5

G3 PWS1

G4 PWS0

/DIRO B6 NC

S1

S0

G5

G6

DP[8:1] B3:E1

E5

E6 CKSI+

CKSI-

DP[9] E2

DP[10] F1

D6

DP[12:11] G1:F2

D5 DSO-/DSI+

C6 DSO+/DSI-

C5 CKSO-

CKSO+

DIRI F6

PLL1 G3

NC

B6

/DIRO

PLL0 G4

S1

G5

S0

G6

VDD2

CMOS Image

Sensor

1.3MPixel

MASTER CLK

PIXEL CLK

DATA[7:0]

HSYNC

VSYNC

/RES

Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)

Serializer Configuration:

ƒ PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range

ƒ PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x

ƒ Master Clock Bypass Mode: (clock passes from CKSI to CKP, see the Strobe Pass-through Mode section)

Deserializer Configuration:

ƒ Edge Rate Mode: Fast MODE 1 (S1=0, S0=1)

ƒ Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period

ƒ Master Clock Bypass Mode: Clock passes from STROBE to CKSO

© 2006 Fairchild Semiconductor Corporation

FIN212AC Rev. 1.0.6

9

www.fairchildsemi.com

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