FIN212AC(2008) 查看數據表（PDF） - Fairchild Semiconductor

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FIN212AC
(Rev.:2008)

12-Bit Serializer Deserializer with Multiple Frequency Ranges

Fairchild Semiconductor 

Power-Down Functionality: When both S1 and S0

signals are 0, regardless of the state of the DIRI

signal, the FIN212AC resets and powers down. The

power-down mode shuts down all internal analog

circuitry, disables the serial input and output of the

device, and resets all internal digital logic. Table 5

indicates the state of the output buffers in Power-

Down mode.

Signal Pins

DIRI=1

DIRI=0

DP[10:1] Inputs Disabled

DP[12:11] Inputs Disabled

CKP

HIGH

STROBE

Input Disabled

CKREF

Input Disabled

/DIRO

0

Table 5. Output States

Outputs HIGH-Z

Outputs HIGH-Z

Outputs HIGH-Z

Input Disabled

Input Disabled

1

When an input is disabled, it does not draw current,

regardless of the state or level of the input signal.

All of the LV-CMOS inputs must remain driven during

power-down to ensure a low-power state

Turn-Around Functionality: The device passes and

inverts the DIRI signal asynchronously to the /DIRO

signal. Care must be taken by the system designer to

ensure that no contention occurs between the

deserializer outputs and the other devices on this port.

Optimally the peripheral device driving the serializer

should be put into a HIGH-impedance state prior to the

DIRI signal being asserted. When a device with

dedicated data outputs turns from a deserializer to a

serializer, the dedicated outputs remain at the last

logical value asserted. This value only changes if the

device is once again turned around into a deserializer

and the values are overwritten.

Strobe Pass-Through Mode: For some applications,

it is desirable to pass a word clock across a

differential signal pair in the opposite direction of

serialization. The FIN212 supports this mode of

operation. The following describes how to enable this

functionality for an images sensor (see Figure 5).

Deserializer Configuration (DIRI=0)

1. Connect CKREF(BGA pin A6) to GROUND

2. Connect master clock to STROBE (BGA pin B5)

Serializer Configuration (DIRI=1)

1. CKSI passes master clock to CKP output (BGA

pin C1)

[CTL_ADJ] CTL Drive Adjustment: The drive

characteristics of the CTL I/O can be adjusted

through the CTL_ADJ pin. Standard-level CTL drive is

provided when the CTL_ADJ pin is zero. High- level

drive is provided when CTL_ADJ pin is HIGH. High-

drive should be used in noisy environments or when

driving cables longer than 20cm. When in high-drive

mode, CTL drive increases by approximately by 50%.

CTL_ADJ

0

Description

Standard CTL Drive

1

High CTL Drive

Table 6. CTL_ADJ Functionality

[(/XTRM]] Test / XTRM Mode Functionality: For the

deserializer, the (XTRM) signal can be used to enable

or disable the internal termination resistor on the CKS

and DS signals of the deserializer. When the internal

termination is disabled, an external termination resistor

is required for the CTL I/O to operate properly.

(XTRM)

DIRI=0 (/XTRM)

0

Internal Termination

1

External Termination

Table 7. (/XTRM) Functionality

© 2006 Fairchild Semiconductor Corporation

FIN212AC Rev. 1.0.6

5

www.fairchildsemi.com

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