FM1808B 查看數據表（PDF） - Cypress Semiconductor

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FM1808B

256Kb Bytewide 5V F-RAM Memory

Cypress Semiconductor 

FM1808B – 256Kb Bytewide 5V F-RAM

A(14:0)

CE

Address

Latch &

Decoder

A(14:0)

32,768 x 8 FRAM Array

Control

WE

Logic

OE

I/O Latch

Bus Driver

DQ(7:0)

Figure 1. Block Diagram

Pin Description

Pin Name

A(14:0)

DQ(7:0)

/CE

/OE

/WE

VDD

VSS

Type

Input

I/O

Input

Input

Input

Supply

Supply

Description

Address: The 15 address lines select one of 32,768 bytes in the F-RAM array. The

address value is latched on the falling edge of /CE.

Data: 8-bit bi-directional data bus for accessing the F-RAM array.

Chip Enable: /CE selects the device when low. Asserting /CE low causes the

address to be latched internally. Address changes that occur after /CE goes low

will be ignored until the next falling edge occurs.

Output Enable: Asserting /OE low causes the FM1808B to drive the data bus when

valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.

Write Enable: Asserting /WE low causes the FM1808B to write the contents of the

data bus to the address location latched by the falling edge of /CE.

Supply Voltage: 5V

Ground

Functional Truth Table

/CE

/WE

Function

H

X

Standby/Precharge

X

Latch Address (and Begin Write if /WE=low)

L

H

Read

L

Write

Note: The /OE pin controls only the DQ output buffers.

Document Number: 001-86209 Rev. **

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