FM24CL16 查看數據表（PDF） - Unspecified

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FM24CL16

16Kb FRAM Serial 3V Memory

Unspecified 

FM24CL16

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read

and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional

relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

tR

tHIGH

tF

tLOW

tSP

tSP

SCL

tSU:SDA

tBUF

SDA

1/fSCL

tHD:DAT

tSU:D AT

Start

Stop Start

tAA

tDH

Acknowledge

Write Bus Timing

SCL

SDA

tSU:STO

t

HD:STA

tHD:DAT

tSU:DAT

Start

Stop Start

tAA

Acknowledge

Data Retention (VDD = 2.7V to 3.65V unless otherwise specified)

Parameter

Min

Units

Data Retention

10

Years

Notes

Rev 2.2

July 2003

Page 11 of 13

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