FM24C04A 查看數據表（PDF） - Ramtron International Corporation
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FM24C04A Datasheet PDF : 12 Pages
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By Master
Start
Address
No
Acknowledge
S
Slave Address 1 A
Data Byte
1P
By FM24C04A
Acknowledge Data
Figure 7. Current Address Read
FM24C04A
Stop
By Master
Start
Address
Acknowledge
No
Acknowledge
S
Slave Address 1 A
Data Byte
A
Data Byte
1P
By FM24C04A
Acknowledge
Data
Figure 8. Sequential Read
Stop
By Master Start
Address
Start
Address
S
Slave Address 0 A
Word Address
AS
Slave Address 1 A
By FM24C04A
Acknowledge
Acknowledge
No
Acknowledge
Stop
Data Byte
A
Data Byte
1P
Data
Figure 9. Selective (Random) Read
Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows and columns. Rows are
defined by A8-A2. Each access causes an endurance
cycle for a row. Endurance is virtually unlimited. At
3000 accesses per second to the same segment, it will
take more than 10 years to reach the endurance limit.
Rev. 3.0
Mar. 2005
7 of 12
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