FM24C04B 查看數據表（PDF） - Ramtron International Corporation
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FM24C04B Datasheet PDF : 12 Pages
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FM24C04B
Figure 7. Current Address Read
Figure 8. Sequential Read
Figure 9. Selective (Random) Read
Endurance
The FM24C04B internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C04B,
a row is 64 bits wide. Every 8-byte boundary marks
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, F-RAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same row, 10 years time will elapse
before 1 trillion endurance cycles occur.
Rev. 1.3
Feb. 2011
Page 7 of 12
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