FM24C64 查看數據表（PDF） - Ramtron International Corporation
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FM24C64 Datasheet PDF : 12 Pages
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Address
By Master Start
DEVICE ADDRESS
No Acknowledge
DATA BYTE
Stop
S
1A
1P
By FM24C64
Acknowledge Data
Figure 7. Current Address Read
FM24C64
Address
By Master Start
DEVICE ADDRESS
DATA BYTE
Acknowledge
DATA BYTE
S
1A
A
A
By FM24C64
Acknowledge
Data
Figure 8. Sequential Read
No Acknowledge
DATA BYTE
Stop
1P
By Master Start
DEVICE ADDRESS
Address
ADDRESS MSB
ADDRESS LSB
Start
DEVICE ADDRESS
S
By FM24C64
0 A XXX
A
AS
1A
Acknowledge
Acknowledge
DATA BYTE
A
No Acknowledge
DATA BYTE
Stop
1P
Data
Figure 9. Selective (Random) Read
Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows which are subdivided
into segments. Rows (defined by A12-A5) are
subdivided into 4 segments (A4-A3). Each access
causes an endurance cycle for a row segment. In the
FM24C64, there are 8 bytes (defined by A2-A0) per
segment. Endurance can be optimized by ensuring
frequently accessed data is located in different
segments. Regardless, FRAM read and write
endurance is effectively unlimited at the 1MHz two-
wire speed. Even at 3000 accesses per second to the
same segment, 10 years time will elapse before 1
trillion endurance cycles occur.
Rev. 3.0
Mar. 2005
7 of 12
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