SN74LS398 查看數據表（PDF） - Motorola => Freescale

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SN74LS398

QUAD 2-PORT REGISTER

Motorola => Freescale 

SN54/74LS398 • SN54/74LS399

AC SETUP REQUIREMENTS (TA = 25°C)

Symbol

tW

ts

ts

th

Parameter

Clock Pulse Width

Data Setup Time

Select Setup Time

Hold Time, Any Input

Limits

Min Typ Max Unit

20

ns

25

ns

45

ns

0

ns

Test Conditions

VCC = 5.0 V

DEFINITIONS OF TERMS

SETUP TIME(ts) — is defined as the minimum time required

for the correct logic level to be present at the logic input prior to

the clock transition from LOW-to-HIGH in order to be recog-

nized and transferred to the outputs.

HOLD TIME(th) — is defined as the minimum time following

the clock transition from LOW-to-HIGH that the logic level

must be maintained at the input in order to ensure continued

recognition. A negative Hold Time indicates that the correct

logic level may be released prior to the clock transition from

LOW-to-HIGH and still be recognized.

AC WAVEFORMS

I0 I1 *

ts(L)

1.3 V

th(L)

CP 1.3 V

Q

tW(L)

tPHL

1.3 V

1.3 V

ts(H)

tW(H)

th(H)

1.3 V

tPLH

1.3 V

Figure 1

S*

1.3 V

ts(L)

CP

1.3 V

1.3 V

th(L) = 0

ts(H)

th(H) = 0

1.3 V

Q or Q

1.3 V

Q = I0

Figure 2

1.3 V

Q = I1

CP

Q

1.3 V

tPHL

1.3 V

1.3 V

1.3 V

tPLH

Q

1.3 V

tPLH

1.3 V

tPHL

Figure 3

*The shaded areas indicate when the input is permitted to change for predictable output performance.

FAST AND LS TTL DATA

5-560

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