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FXL2SD106 查看數據表(PDF) - Fairchild Semiconductor

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FXL2SD106 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DATA
IN
tpxx
DATA
OUT
Vmi
tpxx
VCCI
GND
VCCO
Vmo
Input tR = tF = 2.0ns, 10% to 90%
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 2. Waveform for Inverting and
Non-inverting Functions
OUTPUT
CONTROL
Vmi
tPZL
DATA
OUT
VY
VCCA
GND
VOL
Input tR = tF = 2.0ns, 10% to 90%
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 3. 3-STATE Output Low Enable Time for Low
Voltage Logic
OUTPUT
CONTROL
Vmi
tPZH
DATA
Vx
OUT
VCCA
GND
VOH
Input tR = tF = 2.0ns, 10% to 90%
Input tR = tF = 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
Figure 4. 3-STATE Output High Enable Time for
Low Voltage Logic
Symbol
Vmi(15)
Vmo
VX
VY
Vcc
VCCI / 2
VCCO / 2
0.9 x VCCO
0.1 x VCCO
Note:
15. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2).
©2008 Fairchild Semiconductor Corporation
FXL2SD106 Rev. 1.8.0
9
www.fairchildsemi.com

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