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GS9075A Datasheet PDF : 29 Pages
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GS1575A / GS9075A Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin Number Name
Type
24, 25, 26
SS[2:0]
Bi-directional
Description
When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to
which the PLL has locked.
When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a
selected data rate
.
SS2
SS1
SS0
DATA RATE
SELECTED/FORCED
(Mb/s)
0
0
0
143
0
0
1
177
0
1
0
270
0
1
1
360
1
0
0
540
1
0
1
1483.5/1485
27
ASI/177
Logic Input
When set HIGH, the device disables the 177Mb/s data rate in the data rate
detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI.
When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is
applied, the device could false lock to the 177MHz signal.
28
LOCKED
Output
Lock Detect.
This pin is set HIGH by the device when the PLL is locked.
29
LOS
Output
Loss of Signal.
Set HIGH when there are no transitions on the active DDI[3:0] input. See Lock
and LOS on page 22.
30
VCC_DIG
Power
Most positive power supply connection for the internal glue logic.
Connect to 3.3V.
31
VEE_DIG
Power
Most negative power supply connection for the internal glue logic.
Connect to GND.
33
SD/HD
Output
(GS1575A only)
This signal will be set LOW by the device when the reclocker has locked to
1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e.
the device is not locked).
It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps,
270Mbps, 360Mbps, or 540Mbps.
33
SD
Output
(GS9075A only)
This signal will go HIGH when the reclocker has locked to the input SD signal. It
will be LOW otherwise.
34
KBB
Analog Input
Controls the loop bandwidth of the PLL.
Leave this pin floating for serial reclocking applications.
35
SCO_ENABLE
Power
Serial clock output enable.
Connect to VCC to enable the serial clock output. Connect to GND to disable the
serial clock output.
NOTE: This is not a TTL signal input.
34716 - 0 December 2005
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