GS71108ATPU 查看數據表（PDF） - Unspecified

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GS71108ATPU

128K x 8 1Mb Asynchronous SRAM

Unspecified 

Block Diagram

Truth Table

CE

OE

H

X

L

L

L

X

L

H

Note:

X: “H” or “L”

A0

Row

Decoder

Address

Input

Buffer

A16

CE

WE

OE

Control

Memory Array

Column

Decoder

I/O Buffer

DQ1 DQ8

WE

DQ1 to DQ8

X

Not Selected

H

Read

L

Write

H

High Z

GS71108ATP/J/SJ/U

VDD Current

ISB1, ISB2

IDD

Rev: 1.08 6/2006

2/16

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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