GS8150V18AB 查看數據表（PDF） - Giga Semiconductor
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GS8150V18AB Datasheet PDF : 25 Pages
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GS8150V18/36AB-357/333/300/250
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Typ
Max
DC Input Logic High
VIH (dc)
VREF + 100
—
VDDQ + 300
DC Input Logic Low
VIL (dc)
–300
—
VREF – 100
DC Clock Input Differential Voltage
VDIF (dc)
100
—
VDDQ + 300
VREF DC Voltage
VREF (dc) VDDQ /2 – 0.1
—
VDDQ /2 + 0.1
Clock Input Voltag
VCK (dc)
–300
—
VDDQ + 300
Clock Input Commone Mode Voltage
VCM (dc)
600
750
900
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VDIF).
3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
Units
mV
mV
mV
V
V
V
Notes
2
1
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units Notes
AC Input Logic High
VIH (ac)
VREF + 200
—
mV
3,4
AC Input Logic Low
AC Clock Input Differential Voltage
VIL (ac)
VDIF (ac)
—
VREF – 200
mV
3,4
800
—
mV
2,3
VREF Peak to Peak AC Voltage
VREF (ac)
—
5% VREF (DC)
mV
1
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VDIF). The RAM can be operated with a single ended clocking with
either CK or CK tied to VREF.
3. To guarantee AC characteristics, VIH,VIL,Trise and Tfall of inputs and clocks must be within 10% of each other.
4. For devices supplied with HSTL I/O input buffers.Compatible with both 1.8 V and 1.5 V I/O drivers.
5. See AC Input Definition drawing below.
Rev: 1.04 4/2005
8/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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