GS8170LW36AC-300T 查看數據表（PDF） - Giga Semiconductor
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GS8170LW36AC-300T Datasheet PDF : 32 Pages
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CK
Address
Internal
Address
ADV
/E1
/W
ADV
DQ
CQ
GS8170LW36/72AC-350/333/300/250
SigmaRAM Late Write SRAM Burst Writes with Counter Wrap-around
Write
Continue
Continue
Continue
Continue
A2
XX
XX
XX
XX
XX
A2
A3
A0
A1
A2
Counter Wraps
D2
D3
D0
D1
D2
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th rising edge of clock.
Echo Clock
SRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
Rev: 1.04 4/2005
9/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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