GS9005B 查看數據表（PDF） - Gennum -> Semtech

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GS9005B

GENLINX™ GS9005B Serial Digital Receiver

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Temperature Compensation

Figure 16 shows the connections for the frequency setting

resistors for the various data rates. The compensation shown

for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to

a maximum ambient temperature of 50°C. If the Divide by 2

function is not enabled by the ƒ/2 ENABLE input, no compen-

sation is needed for the 143 Mb/s and 177 Mb/s data rates.

The resistor connections are shown in Figure 17. In both

cases, the 0.1 µF capacitor that bypasses the potentiometer

should be star routed to VEE 3.

1k

10k

0.1µF

VEE

Divide by 2 is OFF

143Mb/s and 177 Mb/s using any RVCO0 pins

5.6k

1.3k

1N914

D 5k

0.1µF

4.3k

1.3k

1N914

5k

0.1µF

E VEE

D Divide by 2 is OFF

N S 270 Mb/s using RVCO0 or RVCO1

VEE

Divide by 2 is ON

143 Mb/s using RVCO2 or RVCO3

E N 1k

1k

M IG 1k

1k

0.1µF

0.1µF

M S 1N914

1N914

O E VEE

C D Divide by 2 is OFF

VEE

Divide by 2 is ON

360 Mb/s using RVCO0 or RVCO1 177 Mb/s using RVCO2 or RVCO3

RE W Fig. 16 Frequency Setting Resistor Values

& Temperature Compensation

E Temperature Compensation Procedure

T N In order to correctly set the VCO frequency so that the PLL will

always re-acquire lock over the full temperature range, the

O following procedure should be used. The circuit should be

N R powered on for at least one minute prior to starting this

procedure.

O Monitor the loop filter voltage at the junction of the loop filter

F resistor and 10 nF loop filter capacitor (LOOP FILTER TEST

Fig. 17 Non - Temperature Compensated Resistor Values

for 143 Mb/s and 177 Mb/s

Loop Bandwidth

The loop bandwidth is dependant upon the internal PLL gain

constants along with the loop filter components connected to

pin 12. In addition, the impedance seen by the RVCO pin also

influences the loop characteristics such that as the imped-

ance drops, the loop gain increases.

Applications Circuit

Figure 18 shows an application of the GS9005B in an

adjustment free, multi-standard serial to parallel convertor.

This circuit uses the GS9010A Automatic Tuning Sub-

system IC and a GS9000B or GS9000S Decoder IC. The

GS9005B may be replaced with a GS9015B Reclocker IC

if cable equalization is not required.

The GS9010A ATS eliminates the need to manually set or

externally temperature compensate the Receiver or Reclocker

VCO. The GS9010A can also determine whether the incoming

data stream is 4ƒsc NTSC,4ƒsc PAL or component 4:2:2.

The GS9010A includes a ramp generator/oscillator which

repeatedly sweeps the Receiver VCO frequency over a set

range until the system is correctly locked. An automatic

fine tuning (AFT) loop maintains the VCO control voltage at

it's centre point through continuous, long term adjustments

of the VCO centre frequency.

When an interruption to the incoming data stream is

detected by the Receiver, the Carrier Detect goes LOW

and opens the AFT loop in order to maintain the correct

VCO frequency for a period of at least 2 seconds. This

POINT). Using the appropriate network shown above, the allows the Receiver to rapidly relock when the signal is re-

VCO frequency is set by first tuning the potentiometer so that established.

the PLL loses lock at the low end (lowest loop filter voltage).

The loop filter voltage is then slowly increased by adjusting the

the potentiometer to determine the error free low limit of the

capture range. Error free operation is determined by using a

suitable CRC or EDH measurement method to obtain a stable

During normal operation, the GS9000B or GS9000S Decoder

provides continuous HSYNC pulses which disable the

ramp/oscillator of the GS9010A. This maintains the

correct Receiver VCO frequency.

signal with no errors. Record the loop filter voltage at this point

as VCL. Now adjust the potentiometer so that the loop filter

voltage is 250 mV above VCL.

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