GTL2002DP 查看數據表（PDF） - Philips Electronics
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GTL2002DP Datasheet PDF : 14 Pages
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Philips Semiconductors
2-bit bi-directional low voltage translator
Product data sheet
GTL2002
PIN CONFIGURATION
GND 1
SREF 2
S1 3
S2 4
8 GREF
7 DREF
6 D1
5 D2
SA00640
Figure 1. SO8 and TSSOP8 pinning
SREF 1
S1 2
S2 3
GND 4
8 GREF
7 DREF
6 D1
5 D2
SA00658
Figure 2. VSSOP8 pinning
PIN DESCRIPTION
PIN NUMBER
SO8 and
TSSOP8
VSSOP8
SYMBOL
NAME AND FUNCTION
1
4
GND Ground (0 V)
2
1
SREF Source of reference transistor
3, 4
2, 3
Sn
Port S1 and Port S2
5, 6
5, 6
Dn
Port D1 and Port D2
7
7
DREF Drain of reference transistor
8
8
GREF Gate of reference transistor
FUNCTION TABLE
HIGH-to-LOW translation assuming Dn is at the higher voltage level
GREF
H
DREF
H
SREF
0V
In-Dn
X
Out-Sn
X
Transistor
Off
H
H
VTT
H
VTT1
On
H
H
VTT
L
L2
On
L
L
0 – VTT
X
X
Off
H = HIGH voltage level
L = LOW voltage level
X = Don’t Care
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input LOW.
3. GREF should be at least 1.5 V higher than SREF for best
translator operation.
4. VTT is equal to the SREF voltage.
FUNCTION TABLE
LOW-to-HIGH translation assuming Dn is at the higher voltage level
GREF
H
DREF
H
SREF
0V
In-Sn
X
Out-Dn Transistor
X
Off
H
H
VTT
VTT
H
H
VTT
L
L
L
0 – VTT
X
H = HIGH voltage level
L = LOW voltage level
X = Don’t Care
H1
nearly off
L2
On
X
Off
NOTES:
1. Dn is pulled up to VCC through an external resistor.
2. Dn follows the Sn input LOW.
3. GREF should be at least 1.5 V higher than SREF for best
translator operation.
4. VTT is equal to the SREF voltage.
CLAMP SCHEMATIC
DREF
GREF
D1
D2
SREF
S1
S2
SA00645
Figure 3. Clamp schematic
2004 Sep 29
3
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