GTL2002DP 查看數據表（PDF） - Philips Electronics

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GTL2002DP

2-bit bi-directional low voltage translator

Philips Electronics 

Philips Semiconductors

2-bit bi-directional low voltage translator

Product data sheet

GTL2002

APPLICATIONS

Bi-directional translation

For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be

connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on DREF is

recommended. The processor output can be totem pole or open drain (pull-up resistors may be required) and the chipset output can be totem

pole or open drain (pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be

uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent

HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference

transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to

5.5 V VCC supply and SREF is set between 1.0 V to VCC – 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the

output of each Dn has a maximum output voltage equal to VCC.

TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION

1.8 V

1.5 V

1.2 V

1.0 V

VCORE

CPU I/O

GTL2002

GND GREF

SREF DREF

S1

D1

S2

D2

200 kΩ

5V

TOTEM POLE OR

OPEN DRAIN I/O

VCC

CHIPSET I/O

INCREASE BIT

SIZE BY USING

10 BIT GTL2010 OR

22 BIT GTL2000

3.3 V

S3

D3

S4

D4

S5

D5

Sn

Dn

VCC

CHIPSET I/O

SA00642

Figure 4. Bi-directional translation to multiple higher voltage levels such as an I2C-bus application

2004 Sep 29

4

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