GTL2003 查看數據表（PDF） - Philips Electronics

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GTL2003

8-bit bidirectional low voltage translator

Philips Electronics 

NXP Semiconductors

GTL2003

8-bit bidirectional low voltage translator

8.2 Unidirectional down translation

For unidirectional clamping, higher voltage to lower voltage, the GREF input must be

connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor

(typically 200 kΩ). A filter capacitor on DREF is recommended. Pull-up resistors are

required if the chip set I/O are open-drain. The opposite side of the reference transistor

(SREF) is connected to the processor core supply voltage. When DREF is connected

through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V

to (VCC − 1.5 V), the output of each Sn has a maximum output voltage equal to SREF.

1.8 V

1.5 V

1.2 V

1.0 V

easy migration to lower voltage

as processor geometry shrinks

VCORE

CPU I/O

200 kΩ

GTL2002

GND

SREF

S1

S2

GREF

DREF

D1

D2

5V

VCC

CHIPSET I/O

totem pole I/O

002aac061

Typical unidirectional HIGH-to-LOW voltage translation.

Fig 5. Unidirectional down translation to protect low voltage processor pins

8.3 Unidirectional up translation

For unidirectional up translation, lower voltage to higher voltage, the reference transistor is

connected the same as for a down translation. A pull-up resistor is required on the higher

voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass

the reference source (SREF) voltage as a HIGH when doing an up translation. The driver

on the lower voltage side only needs pull-up resistors if it is open-drain.

1.8 V

1.5 V

1.2 V

1.0 V

easy migration to lower voltage

as processor geometry shrinks

VCORE

CPU I/O

totem pole I/O

or open-drain

200 kΩ

GTL2002

GND

SREF

S1

S2

GREF

DREF

D1

D2

5V

VCC

CHIPSET I/O

002aac062

Typical unidirectional LOW-to-HIGH voltage translation.

Fig 6. Unidirectional down translation to protect low voltage processor pins

GTL2003_1

Product data sheet

Rev. 01 — 27 July 2007

© NXP B.V. 2007. All rights reserved.

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