H5DU2562GFR 查看數據表（PDF） - Hynix Semiconductor

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H5DU2562GFR

256Mb DDR SDRAM

Hynix Semiconductor 

H5DU2562GFR

DESCRIPTION

The H5DU2562GFR is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main

memory applications which requires large memory density and high bandwidth.

This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

• VDD, VDDQ = 2.5V +/- 0.2V

• All inputs and outputs are compatible with SSTL_2

interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

• x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

• Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

• On chip DLL align DQ and DQS transition with CK

transition

• DM mask write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

• Programmable CAS latency 2/2.5 (DDR200, 266,

333), 3 (DDR400) and 4 (DDR500) supported

• Programmable burst length 2/4/8 with both sequen-

tial and interleave mode

• Internal four bank operations with single pulsed

/RAS

• Auto refresh and self refresh supported

• tRAS lock out function supported

• 8192 refresh cycles/64ms

• 60 Ball FBGA Package Type

• This product is in compliance with the direc-

tive pertaining of RoHS.

ORDERING INFORMATION

OPERATING FREQUENCY

Part No.

H5DU2562GFR-XXC

Configuration Package

16M x 16

60 Ball

FBGA

* X means speed grade

*ROHS (Restriction Of Hazardous Substances)

Grade

- FA

- E3

- J3

- K2

- K3

- L2

Clock Rate

250MHz@CL4

200MHz@CL3, 166MHz@CL2.5,

133MHz@CL2

166MHz@CL2.5, 133MHz@CL2

133MHz@CL2, 133MHz@CL2.5

133MHz@CL2.5, 100MHz@CL2

100MHz@CL2

Remark

(CL-tRCD-tRP)

DDR500 (4-4-4)

DDR400 (3-3-3),

DDR333 (2.5-3-3),

DDR266 (2-3-3)

DDR333 (2.5-3-3)

DDR266A (2-3-3)

DDR266B (2.5-3-3)

DDR200 (2-2-2)

Rev. 1.1 /Sep. 2007

3

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