HD6432611 查看數據表（PDF） - Renesas Electronics

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HD6432611

16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Renesas Electronics 

Item

11.8.3 Register

Descriptions

Page

277,

278

14.3.9 Bit Rate

331

Register (BRR)

Table 14.2

Relationships between

the N Setting in BRR

and Bit Rate B

14.9.7 Notes when 382

Switching from SCK

Pin to Port Pin

15.3.20 HCAN

414

Monitor Register

(HCANMON)

18.2 Module

457

Transitions

Figure 18.2 Flash

Memory State

Transitions

18.9.3 Error

479

Protection

Revision (See Manual for Details)

Bit 7 to 0 description of Input level control/status register

amended

(Before) Pφ/8 clock → (After) φ/8 clock

(Before) Pφ/16 clock → (After) φ/16 clock

(Before) Pφ/128 clock → (After) φ/128 clock

Table 14.2 amended

Mode

Asynchronous

Mode

Clocked

Synchronous

Mode

Smart Card

Interface Mode

Bit Rate

φ × 106

B=

64 × 2 2n-1 × (N + 1)

φ × 106

B=

8 × 2 2n-1 × (N + 1)

φ × 106

B=

S × 2 2n+1 × (N + 1)

Error

φ × 106

Error (%) = { B × 64 × 2 2n-1 × (N + 1) − 1 } × 100

—

φ × 106

Error (%) = { B × S × 2 2n+1 × (N + 1) − 1 } × 100

Problem in Operation

Description amended

(Before) C/A → (After) C/A

Table amended

Bit Bit Name

7 to —

2

Initial Value R/W

Undefined —

Description

Reserved

Only 0 should be written to these bits.

Figure 18.2 amended

(Before) RES = 0 → (After) RES = 0

Description amended

... However, PV1 and EV1 bit setting is enabled, and a

transition can be made to verify mode. ...

Rev. 6.00 Mar 15, 2006 page viii of xxxvi

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