HD64F2643 查看數據表（PDF） - Renesas Electronics
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HD64F2643 Datasheet PDF : 1277 Pages
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Preface
The H8S/2643 Group is a group of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*) and masked ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial
communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also
possible to incorporate an on-chip PC bus interface (IIC) as an option.
In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling
high-speed data transfer without CPU intervention.
Use of the H8S/2643 Group enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.
This manual describes the hardware of the H8S/2643 Group. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology, Corp.
Rev. 3.00 Jan 11, 2005 page v of liv
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