H50335 查看數據表（PDF） - Intersil
零件编号
产品描述 (功能)
生产厂家
H50335 Datasheet PDF : 9 Pages
| |||
HA-5033
Test Circuits and Waveforms (Continued)
500mV
VIN
0V
500mV
VOUT
0V
Schematic Diagram
V+
R5
R4
Q15
Q16
Q19
R6
Q17
Q18
R3
V-
TA = 25oC, RS = 50Ω, RL = 100Ω
PULSE RESPONSE
Q11
Q12
VIN
Q13
Q14
R2
R12
Q6 Q10
R9
Q3
Q4
R8
Q5
Q9
R1
Q1
Q7
R11
VOUT
Q8
R10
Q2
R13
Application Information
Layout Considerations
The wide bandwidth of the HA-5033 necessitates that high
frequency circuit layout procedures be followed. Failure to
follow these guidelines can result in marginal performance.
Probably the most crucial of the RF/video layout rules is the
use of a ground plane. A ground plane provides isolation and
minimizes distributed circuit capacitance and inductance
which will degrade high frequency performance. This ground
plane shielding can also incorporate the metal case of the
HA-5033 since pin #2 is internally tied to the package. This
feature allows the user to make metal to metal contact
between the ground plane and the package, which extends
shielding, provides additional heat sinking and eliminates the
use of a socket, IC sockets contribute inter-lead capacitance
which limits device bandwidth and should be avoided.
4
For the PDIP, pin 6 can be tied to either supply, grounded, or
simply not used. But to optimize device performance and
improve isolation, it is recommended that this pin be grounded.
Other considerations are proper power supply bypassing
and keeping the input and output connections as short as
possible which minimizes distributed capacitance and
reduces board space.
Power Supply Decoupling
For optimum device performance, it is recommended that
the positive and negative power supplies be bypassed with
capacitors to ground. Ceramic capacitors ranging in value
from 0.01µF to 0.1µF will minimize high frequency variations
in supply voltage. Solid tantalum capacitors 1µF or larger will
optimize low frequency performance.
Share Link: 