HAL523SF-A 查看數據表（PDF） - Micronas

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HAL523SF-A

(HAL5xx) Hall Effect Sensor Family

Micronas 

DATA SHEET

HAL 5xy

2. Functional Description

The HAL 5xx sensors are monolithic integrated circuits

which switch in response to magnetic fields. If a mag-

netic field with flux lines perpendicular to the sensitive

area is applied to the sensor, the biased Hall plate

forces a Hall voltage proportional to this field. The Hall

voltage is compared with the actual threshold level in

the comparator. The temperature-dependent bias

increases the supply voltage of the Hall plates and

adjusts the switching points to the decreasing induc-

tion of magnets at higher temperatures. If the magnetic

field exceeds the threshold levels, the open drain out-

put switches to the appropriate state. The built-in hys-

teresis eliminates oscillation and provides switching

behavior of output without bouncing.

Magnetic offset caused by mechanical stress is com-

pensated for by using the “switching offset compensa-

tion technique”. Thus, an internal oscillator provides a

two-phase clock. The Hall voltage is sampled at the

end of the first phase. At the end of the second phase,

both sampled and actual Hall voltages are averaged

and compared with the actual switching point. Subse-

quently, the open drain output switches to the appropri-

ate state. The time from crossing the magnetic switch-

ing level to switching of output can vary between zero

and 1/fosc.

Shunt protection devices clamp voltage peaks at the

output pin and VDD pin together with external series

resistors. Reverse current is limited at the VDD pin by

an internal series resistor up to −15 V. No external

reverse protection diode is needed at the VDD pin for

reverse voltages ranging from 0 V to −15 V.

VDD

1

Reverse

Voltage &

Overvoltage

Protection

Hall Plate

HALL55xxxy

Temperature

Dependent

Bias

Hysteresis

Control

Switch

Comparator

Short Circuit &

Overvoltage

Protection

Output

OUT

3

GND

2

Clock

Fig. 2–1: HAL 5xx block diagram

fosc

t

B

BON

t

VOUT

VOH

VOL

t

IDD

1/fosc = 16 μs

tf

t

Fig. 2–2: Timing diagram

Micronas

Jan. 11. 2010; DSH000020_004EN

7

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