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HC-5504B1(1999) 查看數據表(PDF) - Intersil

零件编号
产品描述 (功能)
生产厂家
HC-5504B1
(Rev.:1999)
Intersil
Intersil Intersil
HC-5504B1 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
HC-5504B1
Applications Diagram
5V TO
12V
SYSTEM CONTROLLER
15
13
14
7 16
RS1 CS1
K1 POWER SWITCH GROUND RING RING
BALANCE NETWORK
DENIAL HOOK KEY SYNC CMD
TIP
8
RD
DETECT DETECT
K1A
RB1
1
TIP
RB2 9
TIP FEED
SLIC
(NOTE 5)
HC-5504B1
21
RX
24
TX
20
+IN
19
C5
C6
C7
R1
ZB
-IN
OP AMP
R3
SUBSCRIBER
LOOP
PRIMARY
PROTEC-
TION
K1B
VB -
10
RING FEED
RS2
3
RING FEED SENSE
R2
18
OUT
C2 17
5
CS2
RB4
2 NEG. BATT. DIG. ANA.
C3
22
C4
RING
PTC
RB3
RING BATT. GND. GND. GND. VB+
+
C4 C3 C2
11
12
6
23
4
C8
C9
+
PCM
FILTER/
CODEC
SWITCHING
NETWORK
Z1
-48V
-48V
150VPEAK (MAX)
RING GENERATOR
VB +
PIN NUMBERS GIVEN FOR DIP/SOIC PACKAGE.
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C2 = 0.15µF, 10V
C3 = 0.3µF, 30V
C4 = 0.5µF to 1.0µF, 10%, 20V (Should be nonpolarized)
C5 = 0.5µF, 20V
C6 = C7 = 0.5µF (10% Match Required) (Note 6)
C8 = 0.01µF, 100V
C9 = 0.01µF, 20V, ±20%
R1 = R2 = R3 = 100k(0.1% Match Required, 1% absolute
value) ZB = 0 for 600Terminations (Note 6).
RB1 = RB2 = RB3 = RB4 = 150(0.1% Match Required, 1%
absolute value).
RS1 = RS2 = 1k, typically.
CS1 = CS2 = 0.1µF, 200V typically, depending on VRING and
line length.
Z1 = 150V to 200V transient protection.
PTC used as ring generator ballast.
NOTES:
5. Secondary protection diode bridge recommended is a 2A, 200V type.
6. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in im-
pedance to within 0.3%. Thus, if C6 and C7 are 1µF each, a 20% match is adequate. It should be noted that the transmit output to C6 sees a -
22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM Fil-
ter/CODEC.
A 0.5µF and 100kgives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within ±5.5V and also has
current limiting protection.
7. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
8. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
60

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