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HCF40104BEY(2002) 查看數據表(PDF) - STMicroelectronics

零件编号
产品描述 (功能)
生产厂家
HCF40104BEY
(Rev.:2002)
ST-Microelectronics
STMicroelectronics ST-Microelectronics
HCF40104BEY Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
HCF40104B
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
s MEDIUM SPEED OPERATION :
12 MHz (Typ.) at 10V
s FULLY STATIC OPERATION
s SYNCHRONOUS PARALLEL OR SERIAL
OPERATION
s THREE-STATE OUTPUTS
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s QUIESCENT CURRENT SPECIF. UP TO 20V
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40104B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP packages.
HCF40104B is a universal shift register featuring
parallel inputs, parallel outputs, SHIFT RIGHT and
SHIFT LEFT serial inputs, and a high-impedance
third output state allowing the device to be used in
bus-organized systems. In the parallel-load mode
(SO and S1 are high), data is loaded into the
DIP
ORDER CODES
PACKAGE
TUBE
DIP
HCF40104BEY
T&R
associated flip-flop and appears at the output after
the positive transition of the CLOCK input. During
loading, serial data flow is inhibited. Shift-right and
shift-left are synchronously accomplished on the
positive clock edge with serial data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs,
respectively. Clearing the register is accomplished
by setting both mode controls low and clocking the
register. When the output enable input is low, all
outputs assume the high impedance state.
PIN CONNECTION
September 2002
1/10

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