HCC4029B 查看數據表（PDF） - STMicroelectronics
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HCC4029B Datasheet PDF : 13 Pages
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HCC/HCF4029B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 KΩ,
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)
Symbol
Parameter
Test Conditions
Value
Unit
VDD (V) Min. Typ. Max.
tPLH Propagation Delay Time (Q Outputs)
tPHL
5
250 500
10
120 240
ns
15
90 180
tPLH Propagation Delay Time (Carry Output)
tPHL
5
280 560
10
130 260
ns
15
95 190
tTLH Transition Time (Q Outputs, Carry Output)
tTHL
5
100 200
10
50 100
ns
15
40 80
tW Minimum Clock Pulse Width
5
90 180
10
45 90
ns
15
30 60
tr, tf ** Clock Rise and Fall Time
5
15
10
15
µs
15
15
tsetup * Minimum Setup Time (Carry Input)
5
30 60
10
10 20
tsetup Minimum Setup Time (B/D or UD)
15
6
12
ns
5
170 340
10
70 140
15
50 100
fmax Maximum Clock Input Frequency
5
2
4
10
4
8
MHz
15
5.5 11
PRESET ENABLE
tPLH Propagation Delay Time (Q Outputs)
tPHL
5
235 470
10
100 200
tPLH Propagation Delay Time (Carry Output)
tPHL
15
80 160
ns
5
320 640
10
145 290
15
105 210
tW Minimum Preset Enable (Pulse Width)
5
65 130
10
35 70
ns
15
25 50
trem * Minimum Preset Enable (Removal Time)
5
100 200
10
55 110 ns
15
40 80
CARRY INPUT
tPHL Propagation Delay Time (Carry Output)
tPLH
5
170 340
10
70 140 ns
15
50 100
tsetup *** Minimum Setup Time (Carry In)
5
25 50
10
15 30
thold Minimum Hold Time (Carry In)
15
12 25
ns
5
100 200
10
35 70
15
* From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge
30 60
** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation
delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load.
*** From Carry in to Clock Edge.
6/13
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