HCPL-0723-560 查看數據表（PDF） - Avago Technologies
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HCPL-0723-560 Datasheet PDF : 12 Pages
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Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time to Logic
Low Output[3]
tPHL
16 22 ns
CL = 15 pF CMOS Signal Levels; Figure 5
Propagation Delay Time to Logic
High Output[3]
tPLH
16 22 ns
CL = 15 pF CMOS Signal Levels; Figure 5
Pulse Width
PW
20 ns
CL = 15 pF CMOS Signal Levels
Maximum Data Rate
Pulse Width Distortion[4] |tPHL - tPLH|
|PWD|
Propagation Delay Skew[5]
tPSK
50
1
2
16
MBd CL = 15 pF CMOS Signal Levels
ns
CL = 15 pF CMOS Signal Levels; Figure 6
ns
CL = 15 pF CMOS Signal Levels
Output Rise Time (10% – 90%)
tR
8 ns
CL = 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%)
tF
6 ns
CL = 15 pF CMOS Signal Levels
Common Mode Transient Immunity
|CMH| 10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic High Output[6] VI = VDD1, VO > 0.8 VDD2
Common Mode Transient Immunity
|CML|
10 15 kV/µs VCM = 1000 V, TA = 25°C,
at Logic Low Output[6] VI = 0 V, VO < 0.8 V
8
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