HCPL-2219-500 查看數據表（PDF） - Avago Technologies
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HCPL-2219-500 Datasheet PDF : 13 Pages
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250
VCC = 5 V
C1 (120 pF) PEAKING
CAPACITOR IS USED.
200 SEE FIGURE 5.
150
tPHL
IF (mA)
5
3
1.6
1.6
3
5
100
tPLH
50
-60 -40 -20 0
20 40 60 80 100
TA – TEMPERATURE – °C
Figure 6. Typical propagation delays vs.
temperature.
PULSE
GENERATOR
ZO = 50 Ω
tr = tf = 5 ns
CL= 15 pF INCLUDING PROBE
AND JIG CAPACITANCES.
VCC
HCPL-2200
VO
+5 V
S1
1
VCC 8
IF
2
7
D1
619 Ω
3
4
INPUT VC
MONITORING
NODE
6
GND 5
CL
D2
5 kΩ
D3
D4
S2
D1-4 ARE 1N916 OR 1N3064.
INPUT
VE
tPZL
OUTPUT
VO
OUTPUT
VO
S1 CLOSED
S2 OPEN
tPZH
S1 OPEN
S2 CLOSED
tPLZ
1.3 V 0.5 V
0.5 V
1.3 V
0V
tPHZ
3.0 V
1.3 V
0V
S1 AND
S2 CLOSED
VOL
VOH
≈1.5 V
S1 AND
S2 CLOSED
Figure 7. Test circuit for tPHZ, tPZH, tPLZ, and tPZL.
100
CL = 15 pF
80
60
tPLZ
40
tPZL
20
VCC
20 V
4.5 V
20 V
4.5 V
0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 8. Typical logic low enable
propagation delay vs. temperature.
200
CL = 15 pF
VCC
150
20 V
tPHZ
4.5 V
100
20 V
50
tPZH
4.5 V
0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 9. Typical logic high enable
propagation delay vs. temperature.
120
VCC = 5 V
C2 = 15 pF
100
80
60
tr
40
20
tf
0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 10. Typical rise, fall time vs.
temperature.
11
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