HCPL-2731WV 查看數據表（PDF） - Fairchild Semiconductor
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HCPL-2731WV Datasheet PDF : 15 Pages
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Isolation Characteristics (TA = 0 to 70°C Unless otherwise specified)
Characteristics
Test Conditions Symbol Min
Input-output
insulation leakage current
Withstand insulation test voltage
Resistance (input to output)
Capacitance (input to output)
Input-Input
Insulation leakage current
Input-Input Resistance
Input-Input Capacitance
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 8)
(RH ≤ 50%, TA = 25°C, II-O ≤ 2 µA)
(Note 4) ( t = 1 min.)
(Note 4) (VI-O = 500 VDC)
(Note 4, 5) (f = 1 MHz)
(RH ≤ 45%, VI-I = 500 VDC) (Note 6)
t = 5 s, (HCPL-2730/2731 only)
(VI-I = 500 VDC) (Note 6)
(HCPL-2730/2731 only)
(f = 1 MHz) (Note 6)
(HCPL-2730/2731 only)
II-O
VISO
RI-O
CI-O
II-I
RI-I
CI-I
2500
** All Typicals at TA = 25°C
Typ** Max
1.0
1012
0.6
0.005
1011
0.03
Unit
µA
VRMS
Ω
pF
µA
Ω
pF
Notes
1. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%.
2. Pin 7 open. (6N138 and 6N139 only)
3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the com-
mon mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode transient
immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
5. For dual channel devices, CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted
together.
6. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
5
Single-Channel: 6N138, 6N139 Dual-Channel: HCPL-2730, HCPL-2731 Rev. 1.0.2
www.fairchildsemi.com
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